Integrated circuit with double dielectric isolation walls

Details Integrated circuit with double dielectric isolation walls Integrated circuit with double dielectric isolation walls

1979-08-24

1982-03-16

Larkins, William D.

357 35, 357 38, 357 92, H01L 2704

Patent

active

043204112

ABSTRACT:
A semiconductor integrated circuit comprising a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, which is of a conductivity type opposite to that of the substrate, a buried layer of a conductivity type opposite to that of the semiconductor substrate, lying between the semiconductor substrate and the epitaxial layer, a dielectric isolation region arranged apart from the buried layer and extending from a surface of the epitaxial layer to the semiconductor substrate, and elements formed in a portion of the epitaxial layer enclosed by the dielectric isolation region. The semiconductor integrated circuit is characterized in that an insulative leakage current blocking region is provided in the portion of the epitaxial layer enclosed by said region, in an arrangement enclosing at least a portion of the elements and extending from the surface of the epitaxial layer to the buried layer.

REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3575646 (1971-04-01), Karcher
patent: 3590345 (1971-06-01), Brewer et al.
patent: 3878551 (1975-04-01), Callahan, Jr.
patent: 3945857 (1976-03-01), Schinella
patent: 3979237 (1976-09-01), Morcom et al.
patent: 4081823 (1978-03-01), Cook
Hamilton & Howard, Basic Integrated Circuit Engineering, McGraw-Hill, N.Y. 1975, pp. 85-88.

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