Patent
1980-05-01
1982-03-16
Edlow, Martin H.
357 41, 357 52, 357 23, H01L 2702
Patent
active
043204090
ABSTRACT:
A CMOS integrated circuit structure having an improved guardband configuration for the prevention of parasitic SCR latchup. Included with each guardband is a pair of field reducing surface regions of the opposite conductivity type to that of the guardband and situated one on each side of the guardband adjacent thereto. The field reducing regions which are electrically connected to each other serve to reduce any electric fields in the bulk region underlying the guardband thereby significantly improving the effectiveness of the guardband for collecting minority carriers in the bulk region to provide greater protection from latchup.
REFERENCES:
patent: 3983620 (1976-10-01), Spadea
patent: 4063274 (1977-12-01), Dingwall
patent: 4161417 (1979-07-01), Yim
patent: 4167747 (1979-09-01), Satow
patent: 4173767 (1979-11-01), Stevenson
patent: 4223334 (1980-09-01), Gasner
patent: 4240093 (1980-12-01), Dingwall
Bell Telephone Laboratories Incorporated
Edlow Martin H.
Torsiglieri Arthur J.
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