Dematrixing circuit of the switched-capacitor type

Details Dematrixing circuit of the switched-capacitor type Dematrixing circuit of the switched-capacitor type

1986-11-19

1988-02-02

Isen, Forester W.

Electrical audio signal processing systems and devices

Binaural and stereophonic

Broadcast or multiplex stereo

358144, H04H 500

Patent

active

047232862

ABSTRACT:
Dematrixing circuit of the switched-capacitor type for dual channel TV stereo sound signals comprising first and second signal inputs (I.sub.1, I.sub.2) for applying a stereo sum signal ##EQU1## thereto and one of the two left and right stereo signals (for example, R), the amplitude of said latter stereo signal being twice as high as that of each of the two stereo signals in the stereo sum signal, and comprising first and second signal outputs (O.sub.1, O.sub.2) for supplying a dematrixed stereo signal. In order to provide the possibility of a correct dematrixing of the stereo signal (L), which is not separately available, with a minimum number of circuit elements and to simultaneously avoid through-connections from the two signal inputs (I.sub.1, I.sub.2) at one end and the two signal outputs (O.sub.1, O.sub.2) at the other end, the dematrixing circuit according to the invention comprises first and second capacitors (C.sub.1, C.sub.2) each being arranged between an input switch (S.sub.i1, S.sub.i2) and an output switch (S.sub.O1, S.sub.O2), said first capacitor (C.sub.1) being arranged via its input (S.sub.i1) and output switches (S.sub.O1) between the first signal input (I.sub.1) and in a first switching phase and between the point of reference potential and a first integrator (INT1) in a second switching phase, said second capacitor (C.sub.2) being arranged via its input and output switches (S.sub.i2, S.sub.O2) in the first switching phase between the second signal input (I.sub.2) and a third capacitor (C.sub.3) which is coupled to the reference potential and in the second switching phase, being short-circuited across the reference potential said third capacitor (C.sub.3) being coupled in a switchable manner via a series switch (S) to the said integrator (INT1), said series switch (S) being opened in the first switching phase and realizing a through-connection in the second switching phase, said first integrator (INT1) being coupled to the first signal input (I.sub.1) and said capacitors (C.sub.1 -C.sub.3) mutually having substantially equal values.

REFERENCES:
patent: 4302837 (1981-11-01), Tanaka et al.
patent: 4472830 (1984-09-01), Nagai
patent: 4512031 (1985-04-01), Van Gils
patent: 4577226 (1986-03-01), Avins
patent: 4644580 (1987-02-01), Akabane

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