Memory decoding circuit

Details Memory decoding circuit Memory decoding circuit

1983-08-31

1988-02-02

Moffitt, James W.

Static information storage and retrieval

Addressing

365189, G11C 800

Patent

active

047232285

ABSTRACT:
Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.

REFERENCES:
patent: 4125878 (1978-11-01), Watanabe
patent: 4386420 (1983-05-01), Ong
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4656610 (1987-04-01), Yoshida et al.
IEEE Journal of Solid-State Circuits--Vol. SC-17, No. 5, Oct. 1982, pp. 863-871.

Affiliated with

Also associated with

Rating

Memory decoding circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory decoding circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory decoding circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1638869