Physical address to logical address translator for memory manage

Details Physical address to logical address translator for memory manage Physical address to logical address translator for memory manage

1990-02-22

1994-01-11

Dixon, Joseph L.

395500, 395575, G06F 1210, G06F 9455, G06F 1130

Patent

active

052789616

ABSTRACT:
Methods and apparatus for translating a physical address to a logical address for use with a processor which includes an on-chip memory management unit. The apparatus includes an address capture circuit which is responsive to information on the processor bus during table searches by the memory management unit for determining logical addresses. A table address is subtracted from a table access address to provide a portion of the logical address during each level of the table search. The logical address portions are combined to provide the complete logical address. The logical address is stored in a map RAM and is accessed when the physical address is requested by the memory management unit. The logical address and corresponding data and status fields are simultaneously provided to an analyzer unit. The apparatus utilizes a pipeline structure for high speed operation.

REFERENCES:
patent: 4482952 (1984-11-01), Akagi
patent: 4636940 (1987-01-01), Goodwin, Jr.
patent: 4825412 (1989-04-01), Sager et al.
patent: 4954942 (1990-09-01), Masuda et al.
patent: 5003459 (1991-03-01), Ramanujan et al.

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