Minimal interrupt latency scheme using multiple program counters

Details Minimal interrupt latency scheme using multiple program counters Minimal interrupt latency scheme using multiple program counters

1992-01-10

1994-05-31

Richardson, Robert L.

395775, G06F 900

Patent

active

053177452

ABSTRACT:
A method and apparatus for using multiple program counters to reduce the latency time of a computer in response to an interrupt or subroutine call using a memory with multiple memory locations for storing the multiple program counters and control means in order to choose which one of the memory locations is used as a current program counter. Additionally, the use of a memory location to store the starting address of the interrupt subroutine is also disclosed.

REFERENCES:
patent: 5123094 (1992-06-01), MacDougall

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