Parallel processor with controllable relation between input and

Details Parallel processor with controllable relation between input and Parallel processor with controllable relation between input and

1995-10-23

1998-09-22

Shah, Alpesh M.

395885, G06F 1580

Patent

active

058128662

ABSTRACT:
In a parallel processor device, at the time specified data is converted to parallel data by the specified unit and processed in parallel and then outputted as serial data, the data is processed and outputted in an arbitrary skipping manner without the necessity of the high speed clock signal. The first pointer mode control means 21 for controlling the address of data writing into data input register is provided, and the number and the interval of the first data when the first data is inputted to the data input register is controlled.

REFERENCES:
patent: 4075691 (1978-02-01), Davis et al.
patent: 4490784 (1984-12-01), Ives et al.
patent: 5475831 (1995-12-01), Yoshida et al.
patent: 5564061 (1996-10-01), Davies et al.
SVP: Serial Video Processor, IEEE 1990 Custom Integrated Circuits, Jim Childers; Peter Reinecke.

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