Phase lock detection in a phase lock loop

Details Phase lock detection in a phase lock loop Phase lock detection in a phase lock loop

1992-10-26

1994-01-11

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331DIG2, H03L 7095, H03L 718

Patent

active

052785203

ABSTRACT:
A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal when the first and second digital input signals have a first logic state at a first transition of a control signal and a second logic state at a second transition of the control signal. One false lock triggers an out-of-phase status indicator. The lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. The first and second digital input signals may operate with a non-50% duty cycle.

REFERENCES:
patent: 4675558 (1987-06-01), Serrone et al.
patent: 5126690 (1992-06-01), Bui et al.
patent: 5161175 (1992-11-01), Parker et al.

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