System and method for transferring data between memories of diff

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395474, 395405, 395308, G06F 1200, G06F 1300

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active

058128166

ABSTRACT:
A system and method for transferring data over a dedicated memory transfer bus between high and low speed memories of a computer system which share a single real memory address space are disclosed. The dedicated memory transfer bus operates independently from the system bus to avoid any adverse effects on bandwidth and latency of the system bus and to allow virtually any memory hierarchy to be selected. The transfer is controlled by the operating system software upon the execution of instructions issued by the memory management unit. Status information such as "invalid" state is used to direct the transfer.

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"Small L2 Options Exclusive Lines", IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1983, pp. 305-306.
"Vertical Partitioning in Cache Hierarchies", IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, pp. 305-306.

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