Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1992-03-12

1994-05-31

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518901, 365238, 365221, G11C 1300

Patent

active

053175409

ABSTRACT:
A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the memory cells in the same column, and serial access control means which serially accesses a plurality of memory cells in a given column of the memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cells storing information, and then sequentially rewrites the bits of information into a different memory cell unused for storing valid data, in the same column where the memory cell exists.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 4070590 (1978-01-01), Ieda et al.
patent: 4225945 (1980-09-01), Kuo
patent: 4593382 (1986-06-01), Fujishima et al.
patent: 4648073 (1987-03-01), Kenney
patent: 4758987 (1988-07-01), Sakui
patent: 4943944 (1990-07-01), Sakui et al.
patent: 4980863 (1990-12-01), Ogihara
patent: 5025294 (1991-06-01), Ema
patent: 5051954 (1991-09-01), Toda et al.
patent: 5079746 (1992-01-01), Sato
patent: 5091761 (1992-02-01), Hiraiwa et al.
patent: 5091885 (1992-02-01), Ohsawa
patent: 5172198 (1992-12-01), Aritome et al.
patent: 5184326 (1993-02-01), Hoffmann et al.
Katsutaka Kimura et al., "A Block-Oriented RAM with Half-Sized DRAM cell and Quasi-Folded Data-Line Architecture" IEEE 1991 ISSCC, Session 6, Paper Tam 612 pp. 106-107.
Arimoto et al., "A Circuit Design of Intelligent CDRAM with Automatic Write back Capability", 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 79-80.
Sha et al., "A 4Mb DRAM with Cross-point Trench Transistor Cell", 1986 ISSCC Digest of Technical Papers, pp. 268-269.
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", 1988 IEDM Technical Digest, pp. 592-595.
Watanabe et al., "Stacked Capacitor Cells for High-density Dynamics RAMs", 1988 IEDM Technical Digest, pp. 600-603.
Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256 M Bit DRAMs", 1989 IEDM Technical Digest, pp. 23-26.
Fujishima et al., "A Storage-Node-Boosted RAM with Word-Line Delay Compensation", IEEE Journal of Solid State Circuits, vol. SC-17, No. 5, pp. 872-875, Oct. 1982.
Ohta et al., "A Novel Memory Cell Architecture for High-Density DRAMs", 1989 Symposium of VLSI Circuits, Digest of Tech. Papers, pp. 101-102.
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High Density VLSI Dynamic Memory", IEEE Transactions on Electron Devices, vol. ED-29, No. 3, Mar. 1982, pp. 368-376.
Ohta et al., "A Novel Memory Cell Architecture for High Density DRAMs", Sharp Technical Journal, vol. 44, Mar. 1990, Japan, pp. 47-50-See Figure 1 and 3.
Asakura et al., "Cell-Plate Line Connecting Complementary Bitline (C3) Architecture for Battery Operating DRAMs", 1991 Symposium on VLSI Circuits, May 30, 1991, pp. 59-60.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1633110