Programmable delay circuit

Details Programmable delay circuit Programmable delay circuit

1983-03-23

1984-07-03

Goldberg, E. A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307603, 3281291, 333138, H03H 730

Patent

active

044581653

ABSTRACT:
A programmable delay circuit comprises input and output multiplexers, a delay device provided between the multiplexers, and a negative feedback path. When the input multiplexer selects an input logic signal, the delay time is controlled by the output multiplexer. When the input multiplexer selects the feedback path, the delay circuit acts as a ring oscillator for generating a square-wave signal whose period is twice the selected delay time. Additional delay devices and multiplexers may be provided between the input and output multiplexers.

REFERENCES:
patent: 3862406 (1975-01-01), Brooks
patent: 4016511 (1977-04-01), Ramsey et al.
patent: 4017747 (1977-04-01), Sheng

Affiliated with

Also associated with

Rating

Programmable delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1632108