Transistor fabrication method

Details Transistor fabrication method Transistor fabrication method

1991-12-23

1994-01-11

Maples, John S.

Fishing, trapping, and vermin destroying

437193, 437200, 148DIG1, 148DIG34, H01L 21441, H01L 2122

Patent

active

052780961

ABSTRACT:
A method of forming p.sup.+ transistor gates is disclosed. A polysilicon layer is covered with an amorphous silicide layer which prevents penetration of p-type dopants through the gate oxide. The silicide may be covered by a dielectric which is formed at a temperature low enough to prevent crystallization of the silicide, a p-type dopant species is directed at the silicide layer. Subsequently an anneal is performed at a temperature high enough to cause a substantial amount of the p-type dopant to move to the polysilicon layer.

REFERENCES:
patent: 4782033 (1988-11-01), Gierisch et al.
patent: 5070038 (1991-12-01), Jin
patent: 5089432 (1992-02-01), Yoo
patent: 5130266 (1992-07-01), Huang et al.
Wolf et al, "Silicon Processing For The VLSI Era," Lattice Press, Sunset Beach, Calif., 1986, pp. 388-392, 325.

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