Single mask process for forming both n-type and p-type gates in

Details Single mask process for forming both n-type and p-type gates in Single mask process for forming both n-type and p-type gates in

1992-08-11

1994-01-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 46, 437983, 148DIG103, H01L 21266

Patent

active

052780856

ABSTRACT:
Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type. The second conductivity type is chosen so as to have minimal counterdoping effect of the previously doped polycrystalline silicon. Wafer processing continues.

REFERENCES:
patent: 4420344 (1983-12-01), Davies et al.
patent: 4966866 (1990-10-01), Mikata et al.
patent: 5021354 (1991-06-01), Pfiester

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