Synchronous dynamic semiconductor memory device capable of restr

Details Synchronous dynamic semiconductor memory device capable of restr Synchronous dynamic semiconductor memory device capable of restr

1997-08-18

1998-09-22

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365 51, 365 63, 36518905, 36523003, G11C 800

Patent

active

058124900

ABSTRACT:
An external clock signal ext.CLK applied to an external clock input pad is transferred to two internal clock generation circuits independent from each other through two independent input first stage circuits. An internal clock signal int.CLK1 controlling the operations of row related circuits and column related circuits is supplied by a first clock generation circuit and an internal clock signal int.CLK2 controlling an output buffer circuit is supplied from a second clock generation circuit.

REFERENCES:
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5687134 (1997-11-01), Sugawara et al.

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