Single-chip synchronous dynamic random access memory (DRAM) syst

Details Single-chip synchronous dynamic random access memory (DRAM) syst Single-chip synchronous dynamic random access memory (DRAM) syst

1997-03-25

1998-09-22

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523004, 36523008, G11C 800

Patent

active

058124896

ABSTRACT:
To use a central processing unit (CPU) operating with a high frequency clock signal, a synchronous dynamic random access memory (DRAM) system includes a signal generator for receiving a first clock signal and second clock signal sequentially, and for outputting a first latch signal after receiving the first clock signal and before receiving the second clock signal, a selecting circuit for selecting a first DRAM cell in a memory cell array in response to a first address signal, and for outputting first data of the first DRAM cell after the first clock signal is received by the signal generator, and a latch circuit for latching the first data when the first latch signal is outputted.

REFERENCES:
patent: 5416746 (1995-05-01), Sato et al.
patent: 5581512 (1996-12-01), Kitamura
patent: 5592434 (1997-01-01), Iwamoto et al.
patent: 5600607 (1997-02-01), Furutani et al.
patent: 5657292 (1997-08-01), McClure
Y. Takai et al.; "250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture"; IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 426-430.

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