Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1992-05-19
1994-05-31
Hudspeth, David R.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307452, 3074821, H03K 19017
Patent
active
053172043
ABSTRACT:
The adverse effects of charge sharing in dynamic logic gates are mitigated. The dynamic logic gates have an inverting buffer for providing a gate output, an arming mechanism for precharging the inverting buffer input, and ladder logic for receiving a gate input and for discharging the inverting buffer input to ground. The ladder logic comprises a plurality of transistors connected in ladder-like manner. In a first embodiment, the interstitial space between parallel transistor gates in the ladder logic is reduced so as to minimize parasitic capacitances. In a second embodiment, the parasitic capacitance of at a converging node defined by at least three converging transistors is minimized by disposing the transistor gates adjacent one another so that the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates. In a third embodiment, a precharger is disposed to inject charge at the converging node when the inverting buffer input is precharged by the arming mechanism. Finally, in a fourth embodiment, the plurality of transistors in the ladder logic are connected in a ladder-like manner exclusively to thereby define a plurality of mutually exclusive paths to ground.
REFERENCES:
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 5015882 (1991-05-01), Houston et al.
Pretorius et al, "Charge Redistribution and Noise Margins in Domino CMOS Logic", IEEE JSSC, vol. CAS-33, No. 8, Aug. 1986, pp. 786-793.
Pretorius et al, "Latched Domino CMOS Logic", IEEE JSSC, vol. SC-21, No. 4, Aug. 1986 pp. 514-522.
Miller, Jr. Robert H.
Yetter Jeffry D.
Hewlett--Packard Company
Hudspeth David R.
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