Electrically-erasable and programmable ROM with pulse-driven mem

Details Electrically-erasable and programmable ROM with pulse-driven mem Electrically-erasable and programmable ROM with pulse-driven mem

1996-07-30

1998-09-22

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518525, 36518526, 36518529, 36518533, G11C 1134

Patent

active

058124586

ABSTRACT:
A memory cell transistor has a floating gate for holding nonvolatile information, a control gate, connected to a word line, for controlling the writing, erasing or reading of information held by the floating gate, and a drain connected to a bit line. Word line drive pulses WDP vibrating alternately between positive and negative potentials are applied to the control gate. When particular data is to be written into the memory cell transistor by means of repeated applications of pulses each having a positive potential corresponding to the particular write data (or when the threshold value of the memory cell transistor is converged to a particular value), bit line potential VBL (drain potential VD) is held low during the initial application of pulse WDP and, as the pulse application is repeated, bit line potential VBL is gradually increased (cf. curve VD3).

REFERENCES:
patent: 4282446 (1981-08-01), McElroy
patent: 4432072 (1984-02-01), Chao et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4649520 (1987-03-01), Eitan
patent: 4797856 (1989-01-01), Lee et al.
patent: 4811292 (1989-03-01), Watanabe
patent: 4931997 (1990-06-01), Mitsuishi et al.
patent: 4953123 (1990-08-01), Takeuchi et al.
patent: 4958317 (1990-09-01), Terada et al.
patent: 5068827 (1991-11-01), Yamada et al.
patent: 5075888 (1991-12-01), Yamauchi et al.
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5126969 (1992-06-01), Kawana
patent: 5132935 (1992-07-01), Ashmore et al.
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5282161 (1994-01-01), Villa
patent: 5283758 (1994-02-01), Nakayama et al.
patent: 5327385 (1994-07-01), Oyama
patent: 5402373 (1995-03-01), Aritome et al.
patent: 5406521 (1995-04-01), Hara
patent: 5412601 (1995-05-01), Sawada et al.
patent: 5491656 (1996-02-01), Sawada
patent: 5602779 (1997-02-01), Gotou
patent: 5615146 (1997-03-01), Gotou
patent: 5623444 (1997-04-01), Gotou et al.
International Electron Devices Meeting. Dec. 8, 1980, Washington, D.C., USA, pp. 602-606, Kupec et al, Triple Level Polysilicon E2PROM with Single Tgransistor Per Bit'.
IEEE Journal of Solid-State Circuits, vol. 29, No. 2, Feb., 1994, pp. 147-150, M. Lanzoni et al, A Novel approach to controlled programming of tunnel-based floating-gate MOSFET's.
IEEE Electron Device Letters, vol. 16, No. 3, Mar., 1995, New Operation Mode for Stacked-Gate Flash Memory Cell, Hiroshi Gotou.

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