Distribution of global variables in synchronous vector processor

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395375, 364DIG1, 3642319, 3642324, G06F 1564

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052936376

ABSTRACT:
A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and the SVP is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided. In order to distribute variables to each processor element simultaneously the data input control circuit is provided with a set of auxiliary registers and an addressing structure to modulate one of the processor elements' working registers. In this manner variables are provided to the SVP device in lieu of a designated control instruction bit.

REFERENCES:
patent: 4688189 (1987-08-01), Novak et al.
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4747081 (1988-05-01), Heilveil et al.
patent: 4757473 (1988-07-01), Kurihara et al.
patent: 4897818 (1990-01-01), Redwine et al.
patent: 4939575 (1990-07-01), Childers
Fisher, Allan L., et al., Architecture of a VLSI SIMD Processing Element, IEEE International Conference on Circuits and Design, 1987, pp. 324-327.
van Rowermud, A. H. M., et al., A General-Purpose Programmable Video Signal Processor, ICCE 1989 VSP/Phillips.
Chin, D., et al., The Princeton Engine: A Real-Time Video System Simulator, IEEE Transactions on Consumer Electronics, vol. 34, No. 2, May 1988, pp. 285-297.
Nakagawa, Shin-ichi, et al., A 50ns Video Signal Processor, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. XXXII, 1989, pp. 168-169, 328.
Kikuchi, Kouichi, et al., A Single-Chip 16-Bit 25ns Realtime Video/Image Signal Processor, IEEE ISSCC Digest of Technical Papers, vol. XXXII, 1989, pp. 170-171, 329.
Wilson, Stephens S., The Pixie-5000-A Systolic Array Processor, IEEE 1985, pp. 477-483.
Davis, Ronald, et al., Systolic Array Chip Matches the Pace of High-Speed Processing, Electronic Design, Oct. 21, 1984, pp. 207-218.
Hannaway, Wyndham, et al., Handling Real-Time Images Comes Naturally to Systolic Array Chip, Electronic Design, Nov. 15, 1984, pp. 289-300.
Smith, Jr.; Winthrop W. et al., Systolic Array Chip Recognizes Visual Patterns Quicker than a Wink, Electronic Design, Nov. 29, 1984, p. 257-266.
Wallis, Lyle, Associative Memory Calls on the Talents of Systolic Array Chip, Electronic Design, Dec. 13, 1984, pp. 217-226.
Fisher, Allan L., et al., Real-Time Image Processing on Scan Line Array Processors, IEEE 1985, pp. 484-489.
Fisher, Allan L., Scan Line Array Processor For Image Computation IEEE 13th Annual International Symposium on Compu. Arch., Compu. Arch. News, vol. 14, No. 2, Jun. 1986, pp. 338-345.
Waltz, David L. Applications of the Connection Machine, IEEE Computer Magazine, Jan. 1987, pp. 85-97.
Webber, Donald M. et al., Circuit Simulation on the Connection Machine, 24th ACM/IEEE Design Automation Conference, 1987, pp. 108-113.
Hillis, W. Daniel, text book excerpt, The Connection Machine, The MIT Press series in artificial intelligence-Thesis (Ph.D.)-MIT, 1985, pp. 18-28.
Fountain, T. J., text book, Integrated Technology for Parallel Image Processing, "Plans for the CLIP7 Chip.", pp. 199-214, Chapter 13.
Gharachlorlo, Nader, et al., A Super Buffer: A Systolic VLSI Graphics Engine for Real-Time Raster Image Generation, 1985 Chapel Hill Conference on VLSI, pp. 285-305.

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