Trenched DMOS transistor fabrication using six masks

Details Trenched DMOS transistor fabrication using six masks Trenched DMOS transistor fabrication using six masks

1992-08-12

1994-05-31

Fourson, George

Fishing, trapping, and vermin destroying

437203, H01L 21336

Patent

active

053169590

ABSTRACT:
A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

REFERENCES:
patent: 5019526 (1991-05-01), Yamane et al.
Chang, T., et al, "Vertical FET . . . Deep Trench Isolation", IBM Tech. Disc. Bull. vol. 22, No. 8B Jan. 1980 pp. 3683-3687.
Ou-Yang, P., "Double Ion Implanted V-MOS Technology", IEEE Journal of Solid State Circuits, vol. SC-12, No. 1, Feb. 1977, pp. 3-8.
International Electron Devices Meeting, 9 Dec. 1990, San Francisco, USA, pp. 793-797, K. Shenai, et al.

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