Flip-flop false output rejection circuit

Details Flip-flop false output rejection circuit Flip-flop false output rejection circuit

1975-03-05

1976-07-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307289, 307291, 328195, H03K 3286, H03K 3353

Patent

active

039719600

ABSTRACT:
An asynchronously timed digital flip-flop circuit eliminates malfunction occurring when internal race conditions cause the flip-flop to lock up at the guasi-stable threshold state in which both input and output signals of the flip-flop are not at true logic levels but are equal to each other. The addition of special circuitry to reject these "false" outputs eliminates their propagation in the digital system in which said flip-flop is employed.

REFERENCES:
patent: 3278758 (1966-10-01), Vroman
patent: 3358238 (1967-12-01), Shapiro et al.
patent: 3603815 (1971-09-01), Rao
patent: 3757231 (1973-09-01), Faustini
patent: 3851189 (1974-11-01), Moyer
patent: 3892985 (1975-07-01), Kawagoe
National Semiconductor Corp. publication; 10/1968; "MM483/MM583 JK Flip-Flops", 4 pages.

Affiliated with

Also associated with

Rating

Flip-flop false output rejection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flip-flop false output rejection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-flop false output rejection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1627020