Patent
1989-06-22
1991-04-23
Mintel, William
357 45, 357 55, 357 51, H01L 2710, H01L 2906, H01L 2702
Patent
active
050103792
ABSTRACT:
A semiconductor memory device includes a p-type semiconductor substrate (1), a trench (16) formed on the substrate (1), a first region (19) of a capacitor cell plate formed on the side walls and the bottom surface of the trench (16) and formed by an n-type impurity layer, two capacitor storage nodes (2a) having their surfaces covered by capacitor dielectric films (7a, 8a) and formed along the side walls of the trench (16) for facing to each other, a second region (3a) of the cell plate formed of an electrically conductive material, the second region (3a) being interposed between the two storage nodes (2a) and connected to the first region (19) of the cell plate at the bottom surface of the trench (16), and n-channel type field effect transistors (9, 10, 12, 18, 28) each connected to one of the storage nodes (2a) and formed on the substrate (1).
REFERENCES:
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4763179 (1988-08-01), Tsubouchi et al.
patent: 4785337 (1989-11-01), Kenney
patent: 4786954 (1988-11-01), Morie et al.
patent: 4922313 (1990-05-01), Tsuchiya
IEEE Journal of Solid State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 909-913, "A Reliable 1-Mbit Dram with a Multi-Bit Test Mode," by Kumanoya et al.
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
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