Semiconductor memory device having on-chip error check and corre

Details Semiconductor memory device having on-chip error check and corre Semiconductor memory device having on-chip error check and corre

1988-02-29

1990-02-20

Atkinson, Charles E.

Excavating

371 211, G06F 1110, G01R 3128

Patent

active

049032682

ABSTRACT:
A semiconductor memory comprises a data bit memory cell array (3), a check bit memory cell array (4), and an address decoder (19) which includes a switching circuit (20) for selectively accessing data from either the memory cell array (3) or (4). Decoding signals d.sub.l to d.sub.m are used for reading out data latched by a column address strobe (CAS) signal. The decoding signals are applied to either the memory cell array (3) or (4) through a group of switching elements selectively rendered conductive by complementary signals .phi. and .phi.. The logical values of the signals .phi. and .phi. change responsive to a change in the CAS signal state.

REFERENCES:
patent: 3988580 (1976-10-01), Warman et al.
patent: 4334309 (1982-06-01), Bannon et al.
patent: 4453251 (1984-06-01), Osman
patent: 4698812 (1987-10-01), Peterson
Chen et al., Error-Correcting Codes for Semiconductor Memory Applications, State-of-the-Art Review, IBM J. Res. Dev., vol. 28, No. 2, Mar. 1984, pp. 124-134.
Quinn et al., Dynamic Testing of Memory Arrays which Utilize ECC Logic, Electronic Engineering, Mar. 1981, pp. 111-119.

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