Patent
1995-02-23
1998-10-27
Voeltz, Emanuel Todd
395707, G06F 945
Patent
active
058288864
ABSTRACT:
A compiling apparatus and method in which instructions are scheduled for an efficient parallel process with a register allotting process and an instruction scheduling process performed independently of each other. An instruction scheduling unit collects information indicating the range of available registers, and renames registers by replacing the register numbers used by the instructions with other register numbers according to the collected register information and the analysis of definition/reference instruction dependency. The instructions are scheduled after the registers have been renamed.
REFERENCES:
patent: 4931928 (1990-06-01), Greenfeld
patent: 5021945 (1991-06-01), Morrison et al.
patent: 5261062 (1993-11-01), Sato
patent: 5404551 (1995-04-01), Katsuno
patent: 5428793 (1995-06-01), Odnert et al.
patent: 5497499 (1996-03-01), Garg et al.
patent: 5557793 (1996-09-01), Senter et al.
Vias et al., "Snooper," Ver 3, ref. man., Vias and Assoc., pp. 26-31, Jan. 1989.
Johnson, Mike "Superscalar Microprocessor Design" Prentice-Hall pp. 9-30, 103-146 Jan. 1991.
Vias et al. "SNOOPER" Version 3 reference manual Vias and Associates pp. 26-31, Jan. 1989.
Corcoran, III Peter J.
Fujitsu Limited
Todd Voeltz Emanuel
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