Transposition memory for a data processing circuit

Details Transposition memory for a data processing circuit Transposition memory for a data processing circuit

1988-07-01

1990-02-20

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1200

Patent

active

049032313

ABSTRACT:
A memory of n.times.n digital data, is adapted to receive the n.times.n data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation.
The memory is constituted by a network of n.times.n registers REG(i,j) and of n.times.n multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period n.times.T. The connections between the memory inputs and outputs and the register network are alternatively connected at the period n.times.T in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.

REFERENCES:
patent: 3535694 (1970-10-01), Anacker et al.
patent: 4302775 (1981-11-01), Widergren et al.
patent: 4791598 (1988-12-01), Liou et al.

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