Single cycle merge/logic unit

Details Single cycle merge/logic unit Single cycle merge/logic unit

1988-11-09

1990-02-20

Williams, Jr., Archie E.

Boots, shoes, and leggings

364947, 3649471, 3649473, 3649476, 3649477, 364950, 3649502, G06F 700, G06F 752, G06F 932

Patent

active

049032283

ABSTRACT:
A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.

REFERENCES:
patent: 3982229 (1976-09-01), Rouse et al.
patent: 4012722 (1977-03-01), Gajski et al.
patent: 4085447 (1978-04-01), Pertl et al.
patent: 4139899 (1976-09-01), Rouse et al.
patent: 4569016 (1986-02-01), Hao et al.
"Processor Unit Mask Generation Control", IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, pp. 6419-6421.
"ALU Merge Operation", IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984, pp. 747-750.

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