Patent
1996-11-13
1998-10-27
Bowler, Alyssa H.
395559, 395555, 39580032, G06F 106
Patent
active
058288686
ABSTRACT:
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
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patent: 5680543 (1997-10-01), Bhawmik
Fletcher Thomas D.
Hinton Glenn J.
Sager David J.
Upton Michael D.
Bowler Alyssa H.
Davis Jr. Walter D.
Intel Corporation
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