Method for fabricating a self-aligned thin-film transistor utili

Details Method for fabricating a self-aligned thin-film transistor utili Method for fabricating a self-aligned thin-film transistor utili

1990-03-21

1991-04-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437101, 437187, 357 237, H01L 2978, H01L 2100

Patent

active

050100270

ABSTRACT:
A method for fabricating self-aligned thin-film transistors (TFTs) includes the steps of: exposing a backside substrate surface, opposite to a principal substrate surface, to ultra-violet (UV) light to cause exposure of at least a photoresist layer portion which corresponds substantially to an area outside the shadow of a gate electrode formed on the principal substrate surface; developing the exposed photoresist portion to form a mask; etching a second insulation layer segment, using the mask, to form a remaining insulation layer segment, which is aligned with the gate electrode, and narrower than the gate electrode by a selected overlap distance, on each side thereof; and forming source and drain electrodes on a doped semiconductor layer which each overlap the gate electrode by the selected overlap distance. The overlap distance is a function of the UV exposure time, the photoresist development time and the etch time of the second insulation layer.

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K. Asama et al., "A Self-Alignment Processed a-Si TFT Matrix Circuit for LCD Panels", Fujitsu Laboratories, Ltd., Atsugi, Japan, pp. 144-145 & 281-285, SID Digest, 1983.
B. Diem et al., "a-Si:H TFT: Potential Suitabilities for Gate and Source-Drain Self-Aligned Structure", pp. 281-285, Mat. Res. Symp. Proc., vol. 33 (1984).
G. E. Possin et al., "Contact-Limited Behavior in Amorphous-Silicon FET for Applications to Matrix-Addressed Liquid-Crystal Displays", pp. 183-189, Proceedings of the SID, vol. 26/3, 1985.

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