Memory access controller having cycle number register for storin

Details Memory access controller having cycle number register for storin Memory access controller having cycle number register for storin

1984-02-23

1986-11-18

Thomas, James D.

Boots, shoes, and leggings

365203, 365236, G06F 1318, G11C 700, G11C 800

Patent

active

046239863

ABSTRACT:
This device permits the distribution of the access to a RAM memory RAM (14) among a plurality of users (U1, U2, U3), the access being effected in an asynchronous manner. Certain users (U2, for example) can access the memory at adjoining addresses by means of a single row precharge cycle, the column access cycles (CAS) being successively effected during a single row (RAS) access cycle. One can thus considerably reduce the access time of the memory (14) when a large quantity of data must be read into the memory or written into it.
Application to teletext terminals where the users of the memory can be the CPU, the video processor, and a teletext data receiver.

REFERENCES:
patent: 4231110 (1980-10-01), Stinehelfer
patent: 4240138 (1980-12-01), Chauvel
patent: 4394753 (1983-07-01), Penzel
patent: 4429375 (1984-01-01), Kobayashi
patent: 4435792 (1984-03-01), Bechtolsheim
patent: 4482949 (1984-11-01), Cates
patent: 4485460 (1984-11-01), Stambaugh
patent: 4485461 (1984-11-01), Kobayashi
patent: 4523277 (1985-06-01), Schnathorst

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