Conditional carry techniques for digital processors

Details Conditional carry techniques for digital processors Conditional carry techniques for digital processors

1985-06-10

1986-11-18

Malzahn, David H.

Boots, shoes, and leggings

364715, 364770, G06F 750

Patent

active

046239820

ABSTRACT:
A relatively small set of cells is shown for constructing a conditional carry adder for two N-digit operands. The structure and organization of the cells is adaptable for constructing any length adder with both high absolute performance and low circuit complexity in LSI by either bipolar or MOS techniques. In addition, the technique is shown adapted for use as either an incrementor or as a priority encoder.

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Millman, Microelectronics, McGraw-Hill Inc. 1979, pp. 170-171.
Sklansky, "Conditional-Sum Addition Logic", IRE Trans. on Electronic Computers, Jun. 1960, pp. 226-230.

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