Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-12-01
1998-10-27
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
36518522, 36518524, 365210, G11C 1134
Patent
active
058286012
ABSTRACT:
A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in V.sub.CC. Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure V.sub.CC remains within strict tolerances. The array cells are programmed and read without resistor biasing and under looser tolerances using the reference cells at a later time.
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Bleiker, "A Four-State EEPROM Using Floating-Gate Memory Cells", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987.
Cleveland Lee E.
Hollmer Shane C.
Advanced Micro Devices , Inc.
Popek Joseph A.
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