Boots – shoes – and leggings
Patent
1996-04-15
1998-10-27
Voeltz, Emanuel Todd
Boots, shoes, and leggings
364488, 364490, 364491, G06F 1750, G06F 1717
Patent
active
058285814
ABSTRACT:
An automatic layout system comprises an input unit to which an LSI design data containing a net list and a cell library data is input, a data processor operating under the control of a program, a memory for storing a first area estimate and a second area estimate, and an output unit. The data processor comprises first decision section which determines a layout style of the LSI, a first area calculation section which performs calculation of the first area estimate upon the presence of I/O cells, a second decision section which determines values of coefficients, a second area calculation section for calculating the second area estimate by using the coefficient in a formula, and a third area calculation section which selects one of the first and second estimates as an output area evaluation. An accurate estimated area can be obtained whether or not given design data is chip data.
REFERENCES:
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5532934 (1996-07-01), Rostoker
Eschermann et al., ("Hierarchical placement for macrocells: a `meet in the middle` approach", IEEE Comput. Soc. Press, IEEE International Conference on Computer-Aided Design, pp. 460-463, 7 Nov. 1988).
Kitazawa et al., (PTO 97-5063, translation of Japanese article, "Statistical Prediction of Block Form in Polycell Layout", Association of Information Processing, 27th Convention of the Information Processing Society of Japan, Jan. 1983, pp. 1479-1480).
Kurdahi et al., ("LAST: a layout area and shape function estimator for high level applications", IEEE Comput. Soc. Press, Proceedings of the European Conference on Design Automation, 25 Feb. 1991, pp. 351-355).
Kurdahi et al., ("Techniques for area estimation of VLSI layouts", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, No. 1, pp. 81-92, Jan. 1989).
Pedram et al., ("Interconnection length estimation for optimized standard cell layouts", IEEE Comput. Soc. Press, 1989 IEEE International Conference on Computer-Aided Design, pp. 390-393, 5 Nov. 1989).
Pedram et al., ("Accurate prediction of physical design characteristics for random logic", IEEE Comput. Soc. Press, Proceedings of the 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 100-108, 2 Oct. 1989).
Sechen, ("Chip-planning, placement and global routing of macro/custom cell integrated circuits using simulated annealing", IEEE, Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 73-80, 12 Jun. 1988).
Upton et al., ("Integrated placement for mixed macro cell and standard cell designs", IEEE, 27th ACM/IEEE Design Automation Conference, 24 Jun. 1990, pp. 32-35).
Kurdahi et al. ("Evaluating layout area tradeoffs for high level applications", IEEE Transactions on Very Large Scale Integration Systems, vol. 1, No. 1, Mar. 1993, pp. 46-55).
"A Statistical Projection of a Block Configurations on Poly-Cell Layout", 27th Convention of the Information Processing Society of Japan, 1983.
Chen et al. ("A module area estimator for VLSI layout", IEEE, Proceedings of 25th ACM/IEEE Design Automation Conference, 12 Jun. 1988, pp. 54-59).
7-88915, "A Statistical Projection of a Block Configuration on Poly-Cell Layout"; 27th Convention of the Information Processing Society of Japan; 1983.
Kik Phallaka
NEC Corporation
Todd Voeltz Emanuel
LandOfFree
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