Computer graphics processing and selective visual display system – Display peripheral interface input device
Patent
1995-07-24
1998-10-27
Liang, Regina
Computer graphics processing and selective visual display system
Display peripheral interface input device
345151, 358532, G09G 504
Patent
active
058283625
ABSTRACT:
A minimum value detecting circuit detects a minimum value among digital R, G, B signals (three primary color signals) for each pixel (one sample) and the minimum value is supplied as a Wht signal (achromatic signal) to a quadruple-speed signal processing circuit. R', G', B' signals (corrected three primary color signals) are generated by subtracting the Wht signal from the R, G, B signals, respectively, and are supplied to the quadruple-speed signal processing circuit. The quadruple-speed signal processing circuit time-division-multiplexes the corrected three primary color signals and the Wht signal to generate a quadruple speed signal. By rendering .pi. cells ON (rotation by 0.degree.) or OFF (rotation by 90.degree.) based upon the time-division-multiplexed signal, a color picture using four time-compressed fields per ordinary field is obtained.
REFERENCES:
patent: 5357353 (1994-10-01), Hirota
Patent Abstracts of Japan, vol. 11, No. 374 (E-562) & JP-A-62 141854 (Fuji Phot Film Co. Ltd), abstract.
Patent Abstracts of Japan, vol. 15, No. 304, (E-1096) & JP-A-03 108982 (FUJITSU), abstract.
Patent Abstracts of Japan, vol. 17, No. 54 (P-1480) & JP-A-04 267246 (FUJITSU), abstract.
Arai Naohisa
Takahashi Takao
Frommer William S.
Liang Regina
Sony Corporation
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