Bus for data processing system with fault cycle operation

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371 32, 371 48, G06F 1300, G06F 1100

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045436282

ABSTRACT:
A digital data processing system including a number of input/output units that communicate with a memory over an input/output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/output unit that initiated the transfer unit to enable it to recover.

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patent: 4348722 (1982-09-01), Gunter et al.
"A Systematic Approach to the Design of Digital Bussing Structures" by K. Thurber et al.; Fall Joint Computer Conference; 1972, pp. 719-740.
Systems Engineering Laboratories, Technical Manual-32/70 Series Computer; Publication No. 303-320070-000; Apr. 1974; pp. 6-1 to 6-8.

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