Multiplexer comprising an N-stage shift register with each stage

Details Multiplexer comprising an N-stage shift register with each stage Multiplexer comprising an N-stage shift register with each stage

1997-01-31

1998-10-27

Wambach, Margaret

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327407, 377 54, 377 75, G11C 1900

Patent

active

058282564

ABSTRACT:
For time division multiplexing N bit-parallel circuit input signals at a high bit rate such as higher than 2.4 Gb/s, where N represents a predetermined integer greater than one, a multiplexer circuit comprises an N-stage shift register (11) for shifting a signal pulse through first to N-th dual output D F/F's (11(1)-11(N)) to produce N master and slave output signals as N stage output signals, N two-input NAND gates (15(1)-15(N)) supplied with the N bit parallel circuit input signals and the N master output signals to produce N gate output signals, an N-input NAND gate (17) multiplexing the N gate output signals into a single gate output signal, and a retiming D F/F (19) for retiming the single gate output signal into a bit-serial circuit output signal. The N slave output signals are delivered respectively to the dual output D F/F's of next stages. Each master output signal is produced by a slave input transfer gate (37) in each dual output F/F comprising master and slave latches master-slave connected together. Preferably, the signal pulse is a negative going pulse. NOR gates may be used instead of the NAND gates.

REFERENCES:
patent: 5570051 (1996-10-01), Chiang et al.
Robert J. Bayruns et al, "a 3GHz 12-channel Time-Division Multiplexer-Demultiplexer Chip Set", 1986 IEEE International Solid-State Circuits Conference, Feb. 20, 1986, Session XV No. 15.4.

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