Three input arithmetic logic unit with shifting means at one inp

Details Three input arithmetic logic unit with shifting means at one inp Three input arithmetic logic unit with shifting means at one inp

1995-06-07

1997-12-09

Kim, Kenneth S.

Boots, shoes, and leggings

36471508, 364736, 395564, 395800, G06F 1700

Patent

active

056969546

ABSTRACT:
A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

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