Process insensitive CMOS window detector

Details Process insensitive CMOS window detector Process insensitive CMOS window detector

1982-09-16

1985-09-24

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307363, H03K 17153, G01R 19165, G01R 29027

Patent

active

045434980

ABSTRACT:
A CMOS window detector provides outputs which indicate whether an input voltage is within a voltage "window". The window detector includes a bias circuit and first and second inverter circuits. A bias current is established by the bias circuit as a function of a reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FETs are connected to the bias circuit to provide two different mirror currents. The mirror currents are a function of the bias current and the current mirror FET channel shape factors. The input voltage signal is applied to the gates of the current control FETs of the first and second inverters. The window voltage level of each inverter circuit is independent of the other inverter circuit and is determined as a function of the mirror current and channel shape factor of the current control FET. Logic level outputs taken from first and second inverter circuits indicate whether an input signal voltage is within or outside the window created by the window voltage levels of the two inverter circuits.

REFERENCES:
patent: 4063119 (1977-12-01), Odell et al.
patent: 4302690 (1981-11-01), Gollinger et al.
patent: 4438349 (1984-03-01), Shoji

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