MESFET process employing dummy electrodes and resist reflow

Details MESFET process employing dummy electrodes and resist reflow MESFET process employing dummy electrodes and resist reflow

1988-11-28

1990-02-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437912, 437982, 437944, 437 41, 437175, 437229, 437 39, 148DIG111, H01L 21283, H01L 21312

Patent

active

049026461

ABSTRACT:
A production method for a semiconductor device (e.g. MESFET) includes a metal pattern production process for producing a plurality of metal patterns e.g. gate, source, drain electrodes on a semiconductor substrate having an active layer. The metal pattern production process includes disposing dummy metal patterns (2a/2b) of silicon nitride at a plurality of metal pattern production regions on the semiconductor substrate using a resist mask (3), disposing a resist pattern (4) on the entire surface of the substrate with gaps between the metal pattern production regions, filling the gaps between said dummy metal patterns and the resist pattern with resist by reflowing the resist pattern (4), removing the dummy metal patterns (2a), depositing a metal layer over the entire surface of the partially completed device, and lifting off unwanted metal to produce a desired metal pattern of source/drain electrodes (5). The second and subsequent steps for replacing the dummy metal pattern with the metal pattern are repeated using another resist pattern (6) to form gate electrode (7).

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Weitzel, C. E., et al., Journal of Electrochemical Society, vol. 133, No. 10, Oct. 1986, pp. 409C-416C.
Yamasaki, K., et al., IEEE Trans. Electron Devices, vol. ED-29, No. 11, Nov. 1982, pp. 1772-1777.
Terada et al, "Self-Aligned Pt-Buried . . . for GaAs LSI", IEEE, GaAs IC Symposium, 1983, pp. 138-141.

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