Memory management unit with address translation function

Details Memory management unit with address translation function Memory management unit with address translation function

1995-09-08

1997-12-09

Moore, David K.

395414, 395415, 395416, 395417, 395418, 395412, G06F 1210, G06F 926, G06F 1200

Patent

active

056969252

ABSTRACT:
Memory management unit with address translation function improves the translation speed for virtual addresses and minimizes the deviation in response time. The memory management unit translates partially and entirely the virtual address into an physical address by using four extended auxiliary caches. And the memory management unit performs table walks for the zest part of the virtual address which is not translated, by using four tables contained in main memory.

REFERENCES:
patent: 4763244 (1988-08-01), Moyer et al.
patent: 4774659 (1988-09-01), Smith et al.
patent: 4800489 (1989-01-01), Moyer et al.
patent: 5319760 (1994-06-01), Mason et al.
patent: 5426750 (1995-06-01), Becker et al.
Sparc Architecture, Cypress Semiconductor, Ross Technology Subsidiary, Sparc Rise User's Guide, Second Edition, Feb. 1990, pp. 4-11.

Affiliated with

Also associated with

Rating

Memory management unit with address translation function does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory management unit with address translation function, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory management unit with address translation function will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1615571