Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1982-09-30
1985-09-24
Newsome, John H.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 86, B05D 306
Patent
active
045432678
ABSTRACT:
A multi-layer semiconductor manufacturing method which employs a plurality of sequentially arranged, adjacent reaction chambers and a plurality of normally closed shutter means respectively separating the reaction chambers. The reaction chambers are each provided with a gas inlet and gas outlet where the reaction chambers each have positioned therein a substrate. The method includes (a) respectively depositing semiconductor layers on the substrates by respectively introducing semiconductor compound gases into the reaction chambers through the gas inlets thereof in such a state that the gases in the reaction chambers are exhausted therefrom through the gas outlets thereof and by respectively applying ionizing electromagnetic fields to the semiconductor compound gases to ionize them into semiconductor compound gas plasmas while at the same time respectively passing semiconductor gas plasmas into the reaction chambers by discharging therefrom the gases, (b) displacing the shutter means and respectively moving the substrates to the next adjacent reaction chambers while removing the substrate in the last chamber, which may be a taking out chamber, while at the same time evacuating entirely the first chamber which may be an insertion chamber, and the remaining reaction chambers or passing therethrough only carrier gases and then closing the shutter means, and (c) positioning a substrate in the first or insertion chamber while at the same time taking out substrate from the last or taking-out chamber to thereby fabricate the multi-layer semiconductor having a plurality of sequentially laminated semiconductor layers.
REFERENCES:
patent: 3472679 (1969-10-01), Ing et al.
patent: 3961103 (1976-06-01), Aisenberg
patent: 4015558 (1977-04-01), Small et al.
patent: 4214926 (1980-07-01), Katsuto et al.
patent: 4223048 (1980-09-01), Engle
patent: 4232057 (1980-11-01), Ray et al.
patent: 4250832 (1981-02-01), Ozaki
patent: 4282267 (1981-08-01), Kuyel
patent: 4282268 (1981-08-01), Priestley et al.
patent: 4328258 (1982-05-01), Coleman
Barber, "IBM Tech. Disc. Bull.", vol. 11, No. 7, 12-1968, pp. 757, 758.
Broosky et al., "IBM Tech. Disc. Bull.", vol. 22, No. 8A, 1-1980, pp. 3391, 3392.
LandOfFree
Method of making a non-single-crystalline semi-conductor layer o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a non-single-crystalline semi-conductor layer o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a non-single-crystalline semi-conductor layer o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1613620