Programmable memory element

Details Programmable memory element Programmable memory element

1997-02-04

1997-12-09

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518505, G11C 1134

Patent

active

056967160

ABSTRACT:
A non-volatile memory element with dual programmable cells and associated read circuit, which comprises a circuit of the bistable type connected between the two memory cells, to which it is coupled through first and second switching circuit elements.
Such switching elements enable a single initial write step by one of the two memory cells only, and thereafter, enable connection of the clear cell and the programmed cell to the bistable circuit.

REFERENCES:
patent: 4802138 (1989-01-01), Shimamune
patent: 4809225 (1989-02-01), Dimmler
patent: 4933906 (1990-06-01), Terada
patent: 5040148 (1991-08-01), Nakai
patent: 5237530 (1993-08-01), Takashina
patent: 5524094 (1996-06-01), Nobukata
Donaldson et al., "SNOS 1K.times.8 Static Nonvolatile RAM," IEEE Journal of Solid-State Circuits SC-17(5):847-851, Oct. 1982.
Gaw et al., "A 100ns 256K CMOS EPROM," in IEEE International Solid-State Circuits Conference, New York, NY, Feb. 14, 1985, pp. 164-165.
Terada et al., "120-ns 128K.times.8-bit/64K.times.16-bit CMOS EEPROM's," IEEE Journal of Solid-State Circuits 24(5):1244-1249, Oct. 1989.

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