High speed multiplier

Details High speed multiplier High speed multiplier

1986-02-10

1988-09-06

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

047697806

ABSTRACT:
A high speed multiplier includes a logic circuit for performing multiplication a multiplicand stored in a first resister and a multiplier stored in a second register, which includes means connected to the second register for selectively gating a selected portion of a multiplier stored in the second register to a recoding means; shift gate means connected to outputs of the first register and controlled by outputs of the recoding means to gate selected groups of multiples of the multiplicand to an adder means for adding a group of multiples of the multiplicand under the control of the control signals; means for accumulating successive intermediate products generated by the adder means; spill adder means, connected to the means for accumulating, for generating a low order portion of a final result of the multiply; storage means for storing the low order portion of the final result; means for generating a high order portion of the final result from outputs of the means for accumulating; and means for storing the high order portion of the final result, wherein the multiplier operates at a rate double the system clock frequency on a 10 bit wide data path on each such double frequency cycle.

REFERENCES:
patent: 3227865 (1966-01-01), Hoernes
patent: 4041292 (1977-08-01), Kindell
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4228520 (1980-10-01), Letteney
patent: 4484301 (1984-11-01), Borgerding et al.
patent: 4546446 (1985-10-01), Machida
Larson, "High-Speed Multiply Using Four Input Carry-Save Adder" IBM Tech. Disclosure Bulletin vol. 16 No. 7 pp. 2053-2054.

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