Integrated logic circuit

Details Integrated logic circuit Integrated logic circuit

1993-03-23

1996-01-30

Voeltz, Emanuel T.

Excavating

364490, 371 204, G06F 1312

Patent

active

054886147

ABSTRACT:
An integrated logic circuit is provided with a plurality of test circuits for performing a Boundary-scan test. Each of the test circuits receives a clock signal, and comprises a first latch circuit for latching supplied data in response to a trailing edge of a clock signal, a second latch circuit for latching output data from the first latch circuit in response to the leading edge of the clock signal and a third latch circuit for latching output data from the second latch circuit in response to the trailing edge of the clock signal. A pulse width of the clock signal is adjusted in accordance with a delay time of the clock signal.

REFERENCES:
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patent: 5210759 (1993-05-01), DeWitt et al.
patent: 5252917 (1993-10-01), Kadowaki
patent: 5271019 (1993-12-01), Edwards et al.
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
IEEE std 1149.1-1990, pp. 1-5.

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