Address conversion for a multiprocessor system having scalar and

Details Address conversion for a multiprocessor system having scalar and Address conversion for a multiprocessor system having scalar and

1985-12-11

1988-09-06

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 936, G06F 900

Patent

active

047697709

ABSTRACT:
An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

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