Scan test circuits for use with multiple frequency circuits

Details Scan test circuits for use with multiple frequency circuits Scan test circuits for use with multiple frequency circuits

1992-12-08

1996-01-30

Beausoliel, Jr., Robert W.

Excavating

371 61, G01R 3128

Patent

active

054886139

ABSTRACT:
A scan path test architecture for testing circuits using multiple system clocks with different frequencies includes a controller (16) for disabling the system clocks during a test cycle and a master clock for generating a signal frequency signal to each circuit module (10a-c), eliminating the need for partitioning scan paths between modules and synchronizing system clocks.

REFERENCES:
patent: 4021784 (1977-05-01), Kimlinger
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4534028 (1985-08-01), Trischler
patent: 4542509 (1985-09-01), Buchanan et al.
patent: 4597080 (1986-06-01), Thatte et al.
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4862068 (1989-08-01), Kawashima et al.
patent: 4870346 (1989-09-01), Mydill et al.
patent: 5008618 (1991-04-01), Van Der Star

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