Arrangement and method for improving room-temperature testabilit

Details Arrangement and method for improving room-temperature testabilit Arrangement and method for improving room-temperature testabilit

1995-08-08

1997-12-09

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324765, 324769, G01R 3126

Patent

active

056964528

ABSTRACT:
Room temperature-testing of an MOS field effect transistor architecture, whose parameters have been optimized for operation at cryogenic temperatures, is facilitated by applying a prescribed reverse body-to-source voltage bias, that modifies the variation of the drain-to-source current vs. gate-to-source voltage characteristic, so as to shift the gate threshold voltage to a value corresponding to the device operating at its optimally designed cryogenic temperature. The magnitude of this back bias voltage is set at a value which adds to the number of charges required to balance the gate voltage before an inversion condition is achieved. In effect, the back bias causes the depletion layer beneath the gate to be expanded into the body beneath the gate, thereby compensating for what would otherwise be depletion mode operation, if the cryogenically designed MOS device were placed at room temperature. This allows the cryogenic performance of the MOS field effect transistor to be tested at room temperature, thereby substantially reducing manufacturing cost. Upon completion of testing of the circuit to evaluate its performance at cryogenic temperatures, the back-bias is removed, so as to allow normal operation in the circuit's intended cryogenic environment.

REFERENCES:
patent: 4916389 (1990-04-01), Hori et al.
patent: 5325054 (1994-06-01), Houston

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