Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Patent
1995-09-13
1997-12-09
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
257355, 257358, 257503, 257546, H01L 2362, H01L 2900
Patent
active
056964048
ABSTRACT:
A manufacturing method for fabricating integrated electronic circuits on a semiconductor support provides a plurality of integrated circuits and provides a plurality of scribing lines. The scribing lines are located such that the electronic circuits are regularly spaced apart by the scribing lines. A network of electrical connection lines is provided in at least one of the scribing lines. Metallization strips are provided in the scribing lines as electrical connection lines, and the electrical connection lines are connected to the integrated circuit. At least one current limitation element is provided between the electrical connection line and the integrated circuit. In this manner it is possible to simultaneously perform electrical testing of all the circuits present on the same wafer.
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patent: 5459688 (1995-10-01), Pfiester et al.
patent: 5466952 (1995-11-01), Moody
patent: 5539325 (1996-07-01), Rostoker et al.
patent: 5548135 (1996-08-01), Avery
"Wafer level test and burn-in," IBM Technical Disclosure Bulletin, 33:8, Jan., 1991, pp. 1-2.
"Wafer burn-in isolation circuit," IBM Technical Disclosure Bulletin, 32:68, Nov., 1989, pp. 442-443.
R. Bove et al., "Impedance terminator for AC testing monolithic chips," IBM Technical Disclosure Bulletin, 15:9, Feb., 1973, pp. 2681-2682.
Marchio Fabio
Murari Bruno
Storti Sandro
Toscani Roberto
Abraham Fetsum
Carlson David V.
SGS--Thomson Microelectronics S.r.l.
Thomas Tom
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