Dynamic programmable logic arrays with NOR-NOR structure impleme

Details Dynamic programmable logic arrays with NOR-NOR structure impleme Dynamic programmable logic arrays with NOR-NOR structure impleme

1987-07-30

1988-09-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307465, 307481, 307585, H03K 19096, H03K 19177

Patent

active

047695625

ABSTRACT:
The blocking circuits which, during precharge, inhibit the data passage to the AND and OR planes of a dynamic programmable logic array with NOR-NOR structure, implemented in C-MOS technology, comprise a pair of transistors with complementary channel doping, the first of which controls the signal passage to the AND or the OR plane, respectively, and the second inhibits the gates of the respective plane during precharge.

REFERENCES:
patent: 4420695 (1983-12-01), Fisher
patent: 4501977 (1985-02-01), Koike
patent: 4569032 (1986-02-01), Lee
patent: 4668880 (1987-05-01), Shoji
patent: 4697105 (1987-09-01), Moy
patent: 4700088 (1987-10-01), Tubbs
patent: 4710650 (1987-12-01), Shoji
"Principles of C-MOS VLSI Design", by N. H. Weste and K. Eshragian, Addison-Wesley, 1985, Chapter 8, pp. 368-379.
"The Design and Analysis of VLSI Circuits", by L. A. Glasser and D. N. Dobberpuhl, Addison-Wesley, 1985, Chapter 7, pp. 383-388.

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