Memory bus interface system

Details Memory bus interface system Memory bus interface system

1981-08-06

1984-05-08

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 306, G06F 1300

Patent

active

044478771

ABSTRACT:
Therein is disclosed high speed digital computer system architecture. System architecture includes a processor for processing machine language digital data and a memory for storing at least machine language instructions for use by the processor. Instructions or data are transmitted between memory and processor by memory input and output busses. Signals are transmitted between computer system and external devices by I/O apparatus. Instruction pre-fetch circuitry is disclosed for fetching from memory, and storing, instructions in advance of instructions being executed by the processor. Also disclosed are a high speed memory and memory input and output busses providing high memory bus bandwidth and simple memory bus interface circuitry. Processor circuitry is disclosed for allowing high speed initiation and execution of instruction sequences. I/O circuitry is disclosed which allows I/O apparatus to easily adapt to a variety of external devices or to changes in computer machine language or instructions.

REFERENCES:
patent: 4093986 (1978-06-01), Bodner et al.
patent: 4117263 (1978-09-01), Yeh

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