Method of manufacturing semiconductor device wherein silicon sub

Details Method of manufacturing semiconductor device wherein silicon sub Method of manufacturing semiconductor device wherein silicon sub

1986-02-03

1987-10-20

Ozaki, George T.

Fishing, trapping, and vermin destroying

148 335, 437915, H01L 21461

Patent

active

047004665

ABSTRACT:
A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200.degree. C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.

REFERENCES:
patent: 2701326 (1955-02-01), Pfann et al.
patent: 2743201 (1956-04-01), Johnson et al.
patent: 3303549 (1967-02-01), Peyser
patent: 4613381 (1986-09-01), Ogura
Japanese Journal of Applied Physics, vol. 17, Supplement 17-1, pp. 275-281, 1978, Azuma, et al.
1983 IEEE IEDM Technical Digest, pp. 79-82, A. M. Goodman, et al.
Originally filed claims in U.S. Ser. No. 809,193, filed Dec. 16, 1985.
Amendment Filed Feb. 25, 1987 in U.S. Ser. No. 809,193.

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