Process for making junction field-effect transistors

Details Process for making junction field-effect transistors Process for making junction field-effect transistors

1986-09-29

1987-10-20

Ozaki, George T.

Fishing, trapping, and vermin destroying

437238, 437 83, H01L 21325, H01L 21425

Patent

active

047004614

ABSTRACT:
A self-aligned integrated JFET device is described wherein an oxide extension region and a doped polysilicon gate is used as part of a self-aligned mask to form drain and source regions. Asymmetric JFETs for power circuit applications can be made in accordance with the invention. Additionally, complementary enhancement mode JFETs can be made in accordance with the invention, for low power consumption and excellent radiation-hardened characteristics.

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